1. Field of the Invention
The present invention relates to a method of fabricating the semiconductor device, and more particularly, to a method of fabricating a semiconductor device having three gates.
2. Description of the Prior Art
A flash memory is a non-volatile memory, which can preserve data within the memory even when an external power supply is off. Recently, because a flash memory is re-writable and re-erasable, it has been widely applied in the fabrication of electrical products, such as mobile phones, digital cameras, video players, personal digital assistants (PDA) or systems on a chip (SOC).
Please refer to FIG. 1, which is a cross sectional diagram illustrating a conventional flash memory cell. As shown in FIG. 1, the flash memory cell 10 includes a semiconductor substrate 12, a gate stack 14 disposed on the semiconductor substrate 12, and a select gate 20 disposed at a side of the gate stack 14. The gate stack 14 includes a floating gate 16 and a control gate 18. The floating gate 16, the control gate 18 and the select gate 20 are commonly made of polysilicon, and the dielectric layers 22/24/26 such as oxide layers are disposed between the gates for electric insulation. The flash memory cell 10 further includes a source region 28 and a drain region 30 disposed in the semiconductor substrate 12 at two sides of the gate stack 14, and a channel region 32 defined in the semiconductor substrate 12 between the source region 28 and the drain region 30. Furthermore, the dielectric layers 22 between the floating gate 16 and the semiconductor substrate 12 may serve as a tunneling oxide, and the hot electrons through the dielectric layers 22 get in or out of the floating gate 16, thereby achieving data accessing.
In the manufacturing process of the conventional flash memory cell 10, two spacer-shaped gate layers (not shown) are previously formed on both sides of the gate stack 14. Subsequently, a mask is used to cover one side of the gate stack, the select gate 20 above the drain region 30 for example, and a reactive-ion-etching (RIE) process is performed to remove the other side of the gate stack 14, the gate layer above the source region 28 for example, to complete the formation of structure of the flash memory cell 10. However, as the size of the flash memory cell 10 is reduced, after the reactive-ion-etching process is completed, some polysilicon residue may remain at the side of the gate stack 14, which is called stringer and referred as stringer R at the side S of the gate stack 14 above the source region 28 as shown in FIG. 1. The stringer R may adversely affect the electrical performances of the flash memory cell, provoke current leakage, and deteriorate the capability of preserving data of the flash memory cell. Consequently, how to avoid the formation of stringer is still an important issue in the field, in order to improve the performances of the flash memory cell.